Article ID Journal Published Year Pages File Type
541003 Integration, the VLSI Journal 2014 11 Pages PDF
Abstract

•Two encoding schemes namely alternating frequency-directed equal-run-length (AFDER) coding and run-length based Hu_man coding (RLHC) are presented.•Multistage encoding schemes for test data compression and test power reductions are presented.•The test application time is reduced as single-stage compression scheme.•The proposed decompression architecture demands only small area overhead.

In this paper, we present two multistage compression techniques to reduce the test data volume in scan test applications. We have proposed two encoding schemes namely alternating frequency-directed equal-run-length (AFDER) coding and run-length based Huffman coding (RLHC). These encoding schemes together with the nine-coded compression technique enhance the test data compression ratio. In the first stage, the pre-generated test cubes with unspecified bits are encoded using the nine-coded compression scheme. Later, the proposed encoding schemes exploit the properties of compressed data to enhance the test data compression. This multistage compression is effective especially when the percentage of do not cares in a test set is very high. We also present the simple decoder architecture to decode the original data. The experimental results obtained from ISCAS'89 benchmark circuits confirm the average compression ratio of 74.2% and 77.5% with the proposed 9C-AFDER and 9C-RLHC schemes respectively.

Related Topics
Physical Sciences and Engineering Computer Science Hardware and Architecture
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