Towards generic charge-pump phase-locked loop, jitter estimation techniques using indirect on chip methods

Due to desirable operational and implementation characteristics, charge-pump phase locked loop (CP-PLL) systems are the architecture of choice for a variety of embedded frequency synthesis applications. A key performance metric of these systems is the spectral purity of the output signal. Spectral purity is difficult to measure directly, especially within a production test environment. This situation is not likely to improve as on-chip system frequencies increase. This paper focuses on specific aspects of a new framework including techniques and methodologies that can detect significant block level errors that lead to spectral degradation. The final crux of the work is to focus towards measurement techniques that can be mapped directly to spectral degradation, and thus prove unambiguously that the CP-PLL system is ‘right by design’ and free from errors without resorting to difficult direct measurements. This paper provides an overview of typical non-idealities and the associated effects on spectral degradation and also provides explanations of suitable detection methods. It is expected that with ever increasing system frequencies, thorough analysis of the relationship between system non-idealities and jitter/phase noise may be the only option available for rapid production testing of fully embedded CP-PLLs.