Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
541683 | Microelectronic Engineering | 2008 | 7 Pages |
Abstract
Charge-pumping (CP) techniques with various rise and fall times and with various voltage swings are used to investigate the energy distribution of interface-trap density and the bulk traps. The charge pumped per cycle (Qcp) as a function of frequency was applied to detect the spatial profile of border traps near the high-k gate dielectric/Si interface and to observe the phenomena of trap migration in the high-k dielectric bulk during constant voltage stress (CVS) sequence. Combining these two techniques, a novel CP technique, which takes into consideration the carrier tunneling, is developed to measure the energy and depth profiles of the border trap in the high-k bulk of MOS devices.
Keywords
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Chun-Yuan Lu, Kuei-Shu Chang-Liao, Chun-Chang Lu, Ping-Hung Tsai, Yin Yin Kyi, Tien-Ko Wang,