Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs

This paper presents a unique scheme for testing and locating multiple stuck at faults in the embedded RAM modules of SRAM-based FPGAs. The RAM modules are tested using the MATS++ algorithm. The interconnection scheme makes it possible to test all the cells within the RAM modules in the FPGA in just one test configuration. We also develop a diagnosis scheme capable of locating the faulty RAM cells and the CLB in which it is located. In this research, emphasis is also laid on reducing the testing time, which is achieved by partitioning the FPGA into two halves.