Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
541842 | Microelectronic Engineering | 2006 | 5 Pages |
Peeling during chemical mechanical polishing (CMP) is investigated with respect to the number of ultra low-k dielectric films in an interconnect stacking. It is shown that the addition of dielectric levels increases significantly the CMP-induced peeling. Stack fracture energies, measured by 4-point bending technique, are relatively less sensitive to the increase of level number, even if a degradation is observed. This leads to the conclusion that delamination during polishing depends highly on the elastic properties of the stack and that there is no simple correlation between stack adhesion and peeling during CMP. In this work, mechanical damages generated in dielectric stack during inter-level CMP were also investigated. It was shown that, if no peeling appears, inter-level CMP have no effect on stack reliability. This indicates that negligible “fatigue” effect, i.e. sub-critical crack growth, takes place during CMP.