Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
541884 | Microelectronic Engineering | 2006 | 5 Pages |
Abstract
Based on electromagnetic approach, electrical models of coupled interconnects surrounded by dummies are extracted, and a simulation procedure in time domain is performed to obtain signal propagation along interconnects representative of the 65 nm CMOS node. This technique is used to quantify effects of size and placement of dummies on parasitic effects such as delay and crosstalk and an optimization of their sizes is proposed.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
B. Blampey, B. Fléchet, A. Farcy, M. Gallitre, C. Bermond, O. Cueto, J. Torres, G. Angénieux,