Low power dynamic logic circuit design using a pseudo dynamic buffer

In this paper, we propose a pseudo dynamic buffer (PDB) for footed domino logic circuit implementation. Using the proposed PDB structure, the output pulse during the precharge process is prevented from propagating to the output stage, as is the case in conventional case. As a result, up to half of the power is saved compared to a conventional domino gate, while improving the sampling window of the dynamic gate. This PDB structure is applicable not only for Pull-down network (N-type) dynamic logic, but also for Pull-up networks (P-type). Simulation results illustrate improved performance using the proposed scheme compared to the conventional dynamic logic for different loading conditions, clock frequencies and logic functions. In addition, our proposed design reduces the clock loading from conventional three to two transistors. As a result, the proposed scheme significantly saves power due to lower load capacitance on the clock bus. Test structures are fabricated in 0.35μm CMOS technology. Measurement results validate the proposed concept and illustrate power saving as compared to conventional design.

► In this paper, we propose a novel footeddomino logic circuit implementation. ► The power consumption of the proposed domino logic is analyzed and compared. ► The simulation result based on 90 nm and 45 nm CMOS technology is provided.