Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
542971 | Integration, the VLSI Journal | 2007 | 8 Pages |
Abstract
This paper presents field programmable gate array (FPGA) implementations of ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efficient combinations of encryption/decryption. The implementations proposed also allow changing the key and encrypt/decrypt (E/D)(E/D) mode for every plain text, without any performance loss. In comparison with other recent block ciphers, the implementation results of ICEBERG show a significant improvement of hardware efficiency. Moreover, the key and E/DE/D agility allow considering new encryption modes to counteract certain side-channel attacks.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
F.-X. Standaert, G. Piret, G. Rouvroy, J.-J. Quisquater,