Electrical characteristics of a vertically integrated field-effect transistor using non-intentionally doped Si nanowires

In this paper, we report the fabrication and the electrical characterization of Vertical Gate All Around Field-Effect Transistors (GAA-FET) using nonintentionally doped Silicon NanoWires (SiNWs) grown by Chemical Vapour Deposition (CVD) using the Vapour–Liquid–Solid (VLS) mechanism as conduction channel. The SiNWs GAA-FET devices exhibited n-channel type semiconductor behaviour whereas the as-grown SiNW FET present p-type behaviour. This effect may be due to positive fixed charge located in the oxide shell or at the Si/SiO2 interface. Moreover we show that the threshold voltage at room temperature is around −0.95 V, a high ION/IOFF ratio up to 106 with a low IOFF current about 1 pA, a maximum transconductance (gm,max ∼ 0.9 μS at VGS = −0.65 V and VDS = 1 V) and a minimum inverse subthreshold slope around 145 mV/decade. In light of these characteristics, these devices can be suitable for high performance, low power consumption components and especially for high density integration in integrated circuits (ICs) interconnections regarding to their 3D architecture.

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