Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
543088 | Microelectronic Engineering | 2010 | 4 Pages |
Abstract
A novel strained SOI process with dual SOI thickness has been demonstrated for the first time. Two different SOI thicknesses (Tsi) are obtained on the same wafer for n- and p-channel devices using one additional photo masking step. Device data shows the S/D junction capacitance is reduced by 12% without any degradation in the driving current. A thicker SOI is used for p-channel devices to increase the SiGe recess depth and volume for the embedded S/D SiGe. The driving current is improved by 15% as a result of the larger compressive stress compared to a smaller SOI thickness. Dual SOI thickness is proved to be a viable strategy for independently optimizing n- and p-channel devices.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
H.C. Lo, C.T. Li, Y.T. Chen, C.T. Yang, W.C. Luo, W.Y. Lu, C.F. Cheng, T.L. Chen, C.H. Lien, H.T. Tsai, M.C. Chen, Samuel K.H. Fung, C.C. Wu,