| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 543103 | Microelectronic Engineering | 2010 | 6 Pages |
By scanning 1/3 nm SiO2/HfSiO(N) gate dielectrics with variable tcharge−tdischarge amplitude charge pumping technique (VT2ACP) and slow rate IdVg hysteresis, we study in detail the energy profile and estimate the spatial position (within SiO2 or HKs layer) of pre-stress and stress-induced electron traps. Pre-stress traps are mainly at shallow energy levels while stress-induced traps are at deeper energy levels. We demonstrate that due to incomplete discharge of bulk traps, the commonly-used base level charge pumping (CP) sweep is not suited for trap energy profiling. Further, we show that in CP measurements, due to the non-negligible tail of the filling probability of traps, even at short charge times, a fraction of HK-bulk traps is scanned in addition to interfacial traps. When the trap density in the HK is significantly higher than in the IL, this fraction might dominate the CP signal and can cause misinterpretation of data. Finally, we point out the possible contribution of the initially-present traps in the formation of a percolation path causing the dielectric breakdown.
