Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
543388 | Microelectronic Engineering | 2009 | 4 Pages |
Abstract
The effect of interface state trap density, Dit, on the device characteristics of n-type, enhancement-mode, implant-free (IF) In0.3Ga0.7As MOSFETs [1] and [2] has been investigated using a commercial drift-diffusion (DD) device simulation tool. Methodology has been developed to include arbitrary Dit distributions in the input simulation decks to more accurately fit the measured subthreshold characteristics of recently reported 1.0 μm gate length IF In0.3Ga0.7As MOSFETs [3]. The impact of interface states on a scaled 30 nm gate length IF MOSFET is also reported.
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
J. Ayubi-Moak, B. Benbakhti, K. Kalna, G.W. Paterson, R. Hill, M. Passlack, I. Thayne, A. Asenov,