| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 543429 | Microelectronic Engineering | 2009 | 6 Pages |
Abstract
This paper discusses recent progress in and challenges of threshold voltage control for advanced high-k/metal-gated (HKMG) devices. It presents the impact on threshold voltage (Vt) control of incorporating La and Al into HKMG devices. A dipole moment model explaining Vt tuning of HfSiON/metal-gated MOSFETs is proposed. In addition, a dual channel scheme that allows La2O3 capping in NMOS and a SiGe channel in PMOS to achieve acceptable Vt for HKMG CMOS devices will be discussed. Also shown is the impact of the robustness of the SiO2/Si interface on the HKMG MOSFET Vt-equivalent oxide thickness (EOT) roll-off. Finally, techniques to improve the interface quality of a HKMG stack will be discussed.
Keywords
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Hsing-Huang Tseng, Paul Kirsch, C.S. Park, Gennadi Bersuker, Prashant Majhi, Muhammad Hussain, Raj Jammy,