Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
543431 | Microelectronic Engineering | 2009 | 4 Pages |
Abstract
We have studied Fermi level pinning (FLP) of Hf-based high-k gate stacks based on thermodynamics based on an O vacancy model. Our study shows that FLP cannot be avoided when the system is under thermal equilibrium. O exposure to aim O vacancy elimination is not effective, since O vacancy elimination condition is equivalent to the Si substrate oxidation which leads to the increase in Equivalent oxide thickness (EOT). We also studied the mechanism of FLP induced by the reduction with H2 anneal. FLP with H2 anneal is governed by the O vacancy annihilation reaction by reducing SiO2 interface layer. Based on these considerations, we propose some recipes for obtaining band-edge-work-function metals.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Kenji Shiraishi,