Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
544042 | Microelectronic Engineering | 2007 | 7 Pages |
The capabilities of energy filtered TEM and EELS/EDS in STEM mode are studied in order to determine the thickness and composition of the sidewall damage layer induced by different plasma patterning processes on a silica-based (SiOC:H) porous material. Concentration profiles are calculated from the obtained energy filtered elemental maps. The sidewall damage layer, typically less than 20 nm thick, has a lower carbon content than the bulk of the low-k layer what leads to an increase of the interline capacitance. In addition to the damage layer, a few nanometers thick carbon rich sidewall polymer layer is observed for some patterning plasma processes. Moreover the bulk composition of the porous low-k layer depends slightly on the used plasma process indicating that not only the sidewalls but also the low-k layer bulk is affected by the process.