| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 544146 | Microelectronic Engineering | 2016 | 5 Pages |
3D integration requires vertical stacking of dies while forming permanent electrical and mechanical connections between the input/output pins of the devices. Through silicon via (TSV) is one of the key elements for 3D integration. This paper presents different liner and barrier/seed approaches for realizing 10 × 100 μm void-free copper filled TSVs. It is found that the plasma enhanced chemical vapor deposition (PECVD) TEOS film shows high dielectric constant, high leakage current and low step coverage. The thermal oxide film offers near 100% step coverage and low leakage current, but the growth rate is very slow. Hence a thermal oxide/PECVD TEOS bi-layer is formed to combine the advantage of each layer. Apart from the conventional plasma vapor deposition (PVD) barrier/seed, a novel metallization scheme with an atomic layer deposition (ALD) barrier and electroless deposited (ELD) seed is also investigated, which shows big potential for further scaling up the aspect ratio of TSV. Finally, a silicon interposer with thousands of TSVs is fabricated and 2.5D integration of device chips is demonstrated, from which good eye diagram is observed.
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