Characteristics of electroplated Sn bumps fabricated without a PR mould on a Si chip for 3D packaging

The characteristics of electroplated Sn bumps, fabricated without a PR (photoresist) mould on copper-plugged TSVs (through-silicon vias), in a Si chip were investigated. A new process of non-PR bumping developed in this research was considered to enhance the productivity and reduce the cost for three-dimensional (3D) chip stacking. To produce Sn bumps, Pt was adopted as an anode, and thinned Si die with Cu-plugged TSVs as a cathode. The polarization curve of the Sn electrolyte was analysed to determine the reduction potential of the Sn ion. The heights, widths, and uniformities of the Sn bumps produced through the proposed non-PR process were evaluated to assess the feasibility of reliable Sn bumping using this process. The experimental results showed that the Sn electrolyte had a reduction potential of −0.463 V. The Sn bumps with rivet-head shapes were produced successfully without a PR mould on Cu-plugged TSV. The Sn bumps grew in both vertical (thickness) and lateral (width) directions due to the absence of a PR mould. The plating time was varied from 2 to 60 min at a constant current density of −30 mA/cm2, and the bump height and width became 39 and 76 μm at 60 min, respectively. The morphologies of the Sn bumps without a PR mould showed the preferred facet growth by increasing the plating time, which resulted in increase of Sn facet size but decrease of number of facets. The uniformity of the bump widths on a chip was within the range of 86.9–95.4%.

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