Analysis of interface trap density of metal–oxide-semiconductor devices with Pr2O3 gate dielectric using conductance method

In this study, the interface trap density of metal–oxide-semiconductor (MOS) devices with Pr2O3 gate dielectric deposited on Si is determined by using a conductance method. In order to determine the exact value of the interface trap density, the series resistance is estimated directly from the impedance spectra of the MOS devices. Subsequently, the dispersion characteristics are numerically analyzed on the basis of a statistical model. Lastly, the process-dependent interface trap density of Pr2O3 is evaluated. It is concluded that high-pressure annealing and a superior quality interfacial SiO2 layer are of crucial importance for achieving a sufficiently low interface trap density.