Article ID Journal Published Year Pages File Type
544544 Microelectronic Engineering 2011 4 Pages PDF
Abstract

The MOSFET gate length reduction down to 32 nm requires the introduction of a metal gate and a high-K dielectric as gate stack, both stable at high temperature. Here we use a nanometric layer of Lanthanum to shift the device threshold voltage from 500 mV. Because this layer plays a key role in the device performance and strongly depends on its deposition process, we have compared two LaOx deposition methods in terms of physical properties and influence on electrical NMOS device parameters. Chemical characterizations have shown a different oxidization state according to Lanthanum thickness deposited. It has been related to threshold voltage shift and gate leakage current variations on NMOS transistors. Furthermore mobility extractions have shown that Lanthanum is a cause of mobility degradation.

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Physical Sciences and Engineering Computer Science Hardware and Architecture
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