Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
544584 | Microelectronic Engineering | 2011 | 6 Pages |
The 300 mm wafer copper electrochemical deposition (ECD) process for dual damascene metallization of semiconductor advanced interconnects is critically reviewed and the breakthroughs that enable further scaling of this process are examined. Special emphasis is placed on analyzing the critical issues, such as barrier/seed options, terminal effect and future plating prospects for this technology. The smallest plateable feature size values are estimated for different metallization integration schemes, such as conventional Physical Vapor Deposited (PVD) TaN/Ta/Cu, hybrid RuTa/Cu, CuMn (8%) self-forming barrier/seed, and Plasma-Enhanced Atomic Layer Deposition (PEALD) Ru, limiting the allowed maximum sheet resistance to 14 Ohms/sq for the Cu-based seeds and the effective maximum filling aspect ratio to 5–6.