| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 544635 | Microelectronic Engineering | 2011 | 4 Pages |
Abstract
Published results on Ge junctions are benchmarked systematically using RS–XJ plots. The electrical activation level required to meet the ITRS targets is calculated. Additionally, new results are presented on shallow furnace-annealed B junctions and shallow laser-annealed As junctions. Co-implanting B junctions with F is shown to degrade junction properties.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Geert Hellings, Erik Rosseel, Trudo Clarysse, Dirch Hjorth Petersen, Ole Hansen, Peter Folmer Nielsen, Eddy Simoen, Geert Eneman, Brice De Jaeger, Thomas Hoffmann, Kristin De Meyer, Wilfried Vandervorst,