Article ID Journal Published Year Pages File Type
544890 Microelectronic Engineering 2009 4 Pages PDF
Abstract

The effects of a Si capping layer on the device characteristics and negative bias temperature instability (NBTI) reliability were investigated for Ge-on-Si pMOSFETs. A Ge pMOSFET with a Si cap shows a lower subthreshold slope (SS), higher transconductance (Gm) and enhanced drive current. In addition, lower threshold voltage shift and Gm,max degradation are observed during NBTI stress. The primary reason for these characteristics is attributed to the improved interface quality at the high-k dielectric/substrate interface. Charge pumping was used to verify the presence of lower density of states in Ge pMOSFETs with a Si cap.

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