Offline Testing of Reversible Logic Circuits: An Analysis

Reversible logic is one of the foregrounds to meet the ever-changing demands electronic devices with its applications to quantum computation. The change in technology gives rise to new challenges; consequently numerous fault model came into the existence where testing plays a significant role to achieve desired results. Several testing methodologies have been proposed for the identification of different types of fault models in reversible logic circuits and are scaled on various performance parameters. We bring collective information of fault models, performance parameters and offline testing approaches from the literature where aim is to obtain a near optimal solution by efficiently exploring the entire space. The paper critically analyses a range of testing strategies reported by the researchers and presented in two broad classifications, namely automatic test pattern generation (ATPG) and design for testability (DFT) methodologies. All the methods are explained in detail with a brief illustration. Comparison results are presented in tabular form highlighting preeminent among all methodologies on the basis of performance parameters.