Analog behavioral equivalence boundary computation under the effect of process variations

Equivalence checking (EC) is a crucial component of integrated circuit (IC) design. EC problem has become even more challenging with the ever-worsening process variations. In our earlier work [10], we researched optimization-based analog equivalence checking (AEC) between Simulink and HSpice models, where we proposed a methodology to find a boundary of equivalence. Although the significance of the effect of process variations is widely accepted, there is limited number of studies addressing the impact of process variations on AEC. In this study, we propose a novel technique to incorporate process variations in AEC. We build a multi-objective optimization problem utilizing evolutionary computation. In this problem, we search for the boundary of equivalence both considering the equivalence value resulting from the effect of process variations and closeness to the boundary. In process variations-effect analysis, we utilize Quasi Monte Carlo (QMC) method to generate samples, which makes it possible to estimate the yield with fewer samples compared to Monte Carlo (MC) method. We generate process variations-aware equivalence boundaries for different equivalence values. We validated our analysis on three designs, an inverter, an operational amplifier, and a buck converter. Our approach proved to be a credible tool for investigating the effect of process variations on the equivalence boundary.