A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power

The power efficiency and reducing the layout area are two main concerns in D-Flip-Flops (D-FF) design. In this paper, a novel architecture is presented for the pulse-triggered D-FF in the CMOS 90-nm technology. This novel architecture utilizes a transmission gate to control the input data and the leakage power. The Pulse Generator (PG) is also modified to reduce the number of required transistors and the clock pulse delay. In addition, the pull-up P-MOS transistor is controlled by input data to reduce the power dissipation. The proposed D-FF is simulated using Hspice. The simulation results show that the proposed architecture has improvement in terms of power consumption, D-to-Q delay, and Power Delay Performance (PDP) in comparison with other D-Flip-Flop architectures.