Article ID Journal Published Year Pages File Type
6942336 Integration, the VLSI Journal 2015 7 Pages PDF
Abstract
In this paper, it is shown that the area optimization problem of a compact slicing floorplan may be formulated as a convex optimization problem when the areas of the analog components are modeled with continuous convex functions of the width (height). It is proved that the area of a compact slicing floorplan is a convex function of its width (height). The convexity is shown for the cases with and without dead (empty) space. This feature can be exploited to efficiently optimize the dimensions of layout components with multiple variants, without enumerating all possible combinations. Layout of a voltage-doubler circuit is used to quantitatively verify the proof.
Related Topics
Physical Sciences and Engineering Computer Science Hardware and Architecture
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