Integration scheme and 3D RC extractions of three-level supervia at 16 nm half-pitch

A multi-level via or 'supervia' (SV) is considered as a scaling booster for the next technology nodes, as it may lower routing resistance and parasitic capacitance as compared to a conventional dual damascene (DD) via. In this paper, we present a three-level SV integration scheme at 16 nm half-pitch along with its 3-D RC extraction. 3-D interconnect geometries are modeled by means of process emulations, performed by using Synopsys' Sentaurus Process Explorer. The resistance of DD vias is also extracted for comparing with SV for various metal and barrier-liner (M-BL) combinations. The R extraction is done based on a resistivity model, calibrated to imec hardware and integrated into Synopsys' Raphael™ tool [1]. Simulations of SV structures with novel M-BL combinations show up to 60% resistance reduction for the investigated interconnect configurations with respect to the DD Cu-TaNCo reference (R = 105 Ω) at a total BL thickness of 3 nm. Furthermore, an approach to compare SV vs DD via capacitance is proposed, which suggests ~16% reduction in parasitic capacitance of SV schemes compared to DD schemes.