| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 6943584 | Microelectronic Engineering | 2015 | 8 Pages |
Abstract
- New materials and device architectures will be needed to extend CMOS scaling.
- High mobility materials in the channel can boost the performance at scaled supply voltage.
- Ultimate reduction of power dissipation will require new concepts like Tunnel FET.
- Vertical devices and 3D stacking allow to further downscale the transistor dimensions.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
N. Collaert, A. Alian, H. Arimura, G. Boccardi, G. Eneman, J. Franco, Ts. Ivanov, D. Lin, R. Loo, C. Merckling, J. Mitard, M.A. Pourghaderi, R. Rooyackers, S. Sioncke, J.W. Sun, A. Vandooren, A. Veloso, A. Verhulst, A.V.-Y. Thean,