| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 6943598 | Microelectronic Engineering | 2015 | 13 Pages |
Abstract
- An overview of strategies to integrate porous layers in microfluidic chips is given.
- Wall coated, membranes, orderly and disorderly coated configurations are discussed.
- Hurdles and challenges to integrate porous layers are discussed.
- Emerging technologies and applications involving surfaced columns are discussed.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Jonas Hereijgers, Gert Desmet, Tom Breugelmans, Wim De Malsche,