Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6943843 | Microelectronic Engineering | 2013 | 5 Pages |
Abstract
Line Edge Roughness (LER) correlation improves the interconnect Time-Dependent Dielectric Breakdown (TDDB) lifetime significantly with respect to non-correlated interconnect based on simulation [M. Stucchi, P. Roussel, Z. TÅkei, S. Demuynck, G. Groeseneken, IEEE Trans. Device Mater. Reliab. 99 (2011)] [1]. On the other hand, 50% Line Edge Roughness (LER) correlation has been observed experimentally after spacer formation in 20Â nm half pitch (HP) interconnects using a Spacer-Defined Double Patterning (SDDP) approach. Comparisons of breakdown field distribution and TDDB lifetime for SDDP patterned 20Â nm HP and Litho-Etch-Litho-Etch (LELE) patterned 35Â nm HP Cu interconnect confirm that the SDDP approach offers potential benefits for TDDB lifetime, which enable future interconnect scaling.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Yong Kong Siew, Michele Stucchi, Janko Versluijs, Philippe Roussel, Eddy Kunnen, Marianna Pantouvaki, Gerald P. Beyer, Zsolt Tokei,