Article ID Journal Published Year Pages File Type
6943843 Microelectronic Engineering 2013 5 Pages PDF
Abstract
Line Edge Roughness (LER) correlation improves the interconnect Time-Dependent Dielectric Breakdown (TDDB) lifetime significantly with respect to non-correlated interconnect based on simulation [M. Stucchi, P. Roussel, Z. Tőkei, S. Demuynck, G. Groeseneken, IEEE Trans. Device Mater. Reliab. 99 (2011)] [1]. On the other hand, 50% Line Edge Roughness (LER) correlation has been observed experimentally after spacer formation in 20 nm half pitch (HP) interconnects using a Spacer-Defined Double Patterning (SDDP) approach. Comparisons of breakdown field distribution and TDDB lifetime for SDDP patterned 20 nm HP and Litho-Etch-Litho-Etch (LELE) patterned 35 nm HP Cu interconnect confirm that the SDDP approach offers potential benefits for TDDB lifetime, which enable future interconnect scaling.
Related Topics
Physical Sciences and Engineering Computer Science Hardware and Architecture
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