| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 6943934 | Microelectronic Engineering | 2013 | 4 Pages |
Abstract
- Si cap passivation on Ge shows low border trap response.
- The Si cap passivation is also suitable for Ge nMOS applications.
- Low Dit at Ec can be achieved by tuning the amount of Si at the interface.
- A dry O3 process can be used to control the amount of Si that is oxidized.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
S. Sioncke, W. Vanherle, W. Art, J. Ceuppens, Ts. Ivanov, D. Lin, L. Nyns, A. Delabie, T. Conard, H. Struyf, S. De Gendt, M. Caymax, N. Collaert, A. Thean,