| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 6944643 | Microelectronic Engineering | 2012 | 4 Pages |
Abstract
⺠Gate-all-around vertically-stacked polySiNW FETs with gate lengths down to 100nm. ⺠ION/IOFF ratio up to 104, subthreshold swings (SS) up to 300 mV/dec. ⺠Excellent step coverage on either finFETs and vertically-stacked SiNW FETs. ⺠Functional inverter and logic NAND operations are obtained.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Davide Sacchetto, Shenqi Xie, Veronica Savu, Michael Zervas, Giovanni De Micheli, Jürgen Brugger, Yusuf Leblebici,