Dual damascene ash development for a VFTL of target k = 2.0 integration

Integration of porous low-k dielectric materials for interconnect technology at the ITRS 45 and 32 nm technology nodes with minimal low-k damage presents many challenges for etch, ash, cleans, and CMP processes. One method of reducing low-k damage is to integrate a MSQ-based dielectric containing a polymer porogen without decomposing the porogen until after copper metallization and CMP [White et al., Proceedings of the Advanced Metallization Conference, 2004, p. 122; M. Fayolle et al., Proceedings of the IITC, 2004, p. 208]. Maintaining a dense film through these critical processes, potentially solves the problems of low-k damage due to etch, ash and clean interactions with a porous structure as well as preserving copper barrier conformality. However, this integration holds major challenges for ash processes due to the requirements for the spin-on hardmask material used here, which has a high ash rate compared to CVD materials. Also trying to remove resist, BARC and etch polymer without interacting with either the MSQ matrix or polymer porogen proves difficult. We show how an optimized N2/H2 ash can be used for the via and trench level ash processes for the VFTL integration scheme. A variety of plasma-based lithography rework processes were also investigated with limited success. A dense layer film (CVD or metal hard-mask) may be necessary to enable lithography rework processing.