Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
9670329 | Microelectronic Engineering | 2005 | 7 Pages |
Abstract
We developed a 65-nm CMOS technology that could successfully integrate a novel porous low-k material, NCS. Using our nano-clustering technique, we obtained that NCS had a high compatibility between a very low dielectric constant and high framework strength. We successfully fabricated 11-levels Cu interconnects using hybrid-NCS structure. These interconnects had a high tolerance to the etching process and produced a smooth surface on the bottom of the trenches, with no via-fences, and no low-k voiding. They did not require a pore-sealing process. These high-performance hybrid-NCS/Cu multilevel interconnects met the 65-nm node requirements for Back-End of the Line, while maintaining sufficient robustness to support CMP, wire-bonding, and packaging processes. Hybrid-NCS/Cu multilevel interconnects are suitable for mass production and show excellent reliability for 65-nm node device requirements.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
I. Sugiura, N. Misawa, S. Otsuka, N. Nishikawa, Y. Iba, F. Sugimoto, Y. Setta, H. Sakai, Y. Koura, K. Nakano, T. Karasawa, Y. Ohkura, T. Kouno, H. Watatani, Y. Nakata, Y. Mizushima, T. Suzuki, H. Kitada, K. Watanabe,