Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
9670342 | Microelectronic Engineering | 2005 | 7 Pages |
Abstract
TiSi, CoSi, CoSi2 and NiSi are used for a salicide contact metallisation in DRAM devices. The contact resistance is studied: for contacts to tungsten silicide-gates, for self-aligned n-type contacts in the memory cell array and for large borderless n-type and p-type contacts in the chip periphery. It is shown that the contact resistance on p-type contacts is reduced with CoSi by at least 40% compared to TiSi and NiSi, whereas the contact resistance of cell array-, gate- and n-type contacts is comparable for the different silicides. In order to enable a sufficient retention time the leakage current is critical. Due to the low silicon consumption NiSi contacts result in the smallest leakage. Using a Cobalt + Ti-Cap stack the Si leakage currents rise by orders of magnitude. It is shown that with a TiN-cap and a changed chemistry for the selective strip leakage currents as small as for TiSi can be achieved. The role of CoSi-thickness and the formed silicide-phase, i.e., CoSi or CoSi2, on contact resistance and leakage current are discussed.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
C. Fitz, M. Goldbach, A. Dupont, S. Schmidbauer,