Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
9670352 | Microelectronic Engineering | 2005 | 5 Pages |
Abstract
3D Integration of CMOS transistors with ICV-SLID technology is reported in this paper. NMOS and PMOS metal gate transistor devices have been further processed by forming deep trench inter-chip-vias and by thinning the substrate to 25 μm remaining silicon thickness. No degradation of transistor behavior found due to the additional 3d-processing steps. Results of the process flow and electrical measurements of transistors on thin silicon are shown in this paper.
Keywords
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Robert Wieland, Detlef Bonfert, Armin Klumpp, Reinhard Merkel, Lars Nebrich, Josef Weber, Peter Ramm,