Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
9670468 | Microelectronic Engineering | 2005 | 8 Pages |
Abstract
The thermal budget involved in processing high-k gate stacks can cause undesirable physical and chemical changes which limit device performance. The transmission electron microscope and associated analytical techniques provide a way of investigating these changes on a sub-nanometre scale. Using electron energy loss near edge structure (ELNES), information on the local chemistry may be extracted. These techniques are applied to high-k dielectric stacks grown on Si and containing HfO2 and HfSiO layers.
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Physical Sciences and Engineering
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Authors
A.J. Craven, M. MacKenzie, D.W. McComb, F.T. Docherty,