Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
9670520 | Microelectronic Engineering | 2005 | 8 Pages |
Abstract
The introduction of ultra low-k materials in copper technology has been much slower than anticipated in the ITRS Roadmap. The introduction of porosity in low-k materials has increased the level of complexity tremendously. In this paper, the challenges appearing during the integration of ultra low-k dielectrics will be discussed, since a proper understanding of these issues is essential for downscaling of the interconnect system. The inferior mechanical and thermal properties were always identified as main showstoppers for low-k integration. However, the extreme vulnerability of porous low-k to produces-induced damage (accompanied with the loss of dielectric performance and reliability) demands a continuous innovation of materials, processes and integration approaches.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
R.J.O.M. Hoofman, G.J.A.M. Verheijden, J. Michelon, F. Iacopi, Y. Travaly, M.R. Baklanov, Zs. Tökei, G.P. Beyer,