Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
9670658 | Microelectronic Engineering | 2005 | 9 Pages |
Abstract
A rapidly responding yet highly accurate on-chip interconnect simulation model, an optimal cascade lumped model, is presented. Compared with previous interconnect simulating models with similar parameters, the new model expends less CPU time and provides simple closed-form expressions for accurate number of repeated RLCG or LC models, which are proved by the simulation results of 0.18, 0.13, 0.07 and 0.05 μm. It is valuable to guide the analysis and the simulation of deep submicron VLSI circuits with billions of interconnects.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Ma Qungang, Yang Yintang, Li Yuejin, Jia Xinzhang,