Non-destructive high-resolution characterization of buried interfaces for advanced interconnect and packaging architectures: Experiments and modeling

Characterization of buried interfaces in advanced interconnect and packaging structures is a critical challenge as complementary metal-oxide-semiconductor (CMOS) devices are scaled and as novel packaging and interconnect concepts and materials such as three-dimensional (3-D) circuits, and ultra-low dielectric constant insulators are developed. Critical information that needs to be obtained from such inspection includes detection of unbonded bumps in flip-chip packages; missing interconnections in bonded wafers and presence of delaminations in interconnect layers. In this paper, we discuss in detail our experimental and theoretical investigation of different non-destructive characterization techniques namely acoustic imaging, infra-red imaging and transient thermal microscopy to analyze and quantify the quality of buried interfaces. The imaging resolution is shown to critically depend on the material thickness through which the incident probe beam has to propagate to form the images. Defects in buried interfaces such as voids in bonded wafers appear as regions of bright contrast in acoustic imaging due to large acoustic impedance mismatch at the voids. In the case of transient thermal microscopy, unbonded areas will lead to non-uniform temperature distribution at the surface of the substrate when the sample is rapidly heated with a flash lamp. The localized temperature rise at the defect and its temporal evolution can be related in turn to the defect size. We discuss capabilities and limitations of the different techniques for inspection of buried interfaces with an emphasis on characterizing bonded interfaces for 3-D integrated circuits. It is shown that acoustic imaging with single spherical lens is better suited to study bond quality compared to thermal microscopy due to its better detection capabilities. Infra-red imaging was found to be unsuitable for investigation of bonded interfaces in wafers containing multiple layers of metallization.