Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
4970761 | Microelectronic Engineering | 2017 | 15 Pages |
Abstract
Description of different SiGe samples (300Â mm SOI wafer) under study: 1) initial silicon bulk used as a reference material, 2) SiGe layer grown by epitaxy (channel layer), 3) nitride silicon deposition (low-k dielectric layer), 4) silicon nitride etching, 5) surfaces cleaned by various processes, 6) SiGe:B layer grown by epitaxy (Raised-Source-Drain epitaxy).135
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Authors
M. Labrot, F. Cheynis, D. Barge, P. Maury, M. Juhel, S. Lagrasta, P. Müller,