Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
539805 | Microelectronic Engineering | 2014 | 9 Pages |
•Si3N4 and SiO2 double passivation is deposited top and bottom of T gate.•0.1 μm gate length realisation using double exposure e-beam lithography.•Wide gate recess process increases DC properties.•High power density of 2.4 W/mm for Ka-band high frequency application.
In this study, a novel manufacturing process for a 0.1 μm T-gate is investigated for producing a high output power performance for the Ka-band frequencies using high-quality AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors (PHEMTs) on semi-insulated (SI) GaAs substrates. The gate manufacturing process is the most important process due to its intimate relationship with the DC and RF performance of the device. To improve the gate performances of PHEMT devices, we investigated various materials and processing approaches involving a wide gate recess, double exposure by e-beam lithography, and low-damage double-gate passivation methods based on plasma-enhanced chemical vapour deposition (PECVD). To reduce the sensitivity to current collapse effects, we investigate the relationship between the electrical characteristics of the PHEMTs and top and bottom gate-supported passivation films. To improve the ohmic contact performance, we test an AuGe/Ni/Au (200/30/120 nm) ohmic contact metallisation scheme using the rapid thermal annealing (RTA) process at temperatures ranging from 450 °C 30 s. A PHEMT with a gate length of 0.1 μm, exhibiting a maximum drain current density of 680 mA/mm, a peak transconductance of 500 mS/mm, a unity-gain cut-off frequency (fT) of 56 GHz, and a maximum frequency of oscillation (fMAX) of 84 GHz, is demonstrated using this novel manufacturing process; the Ka-band power performance includes an output power density of 2.4 W/mm and a power-added efficiency (PAE) of 44.6%.
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