Article ID Journal Published Year Pages File Type
539857 Microelectronic Engineering 2010 5 Pages PDF
Abstract

A 32 nm node BEOL integration scheme is presented with 100 nm metal pitch at local and intermediate levels and 50 nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32 nm RC performance specifications, extreme low-k (ELK) porous SiOCH k = 2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k = 2.3 is investigated using a multi-level metallization test vehicle in a 45 nm mature generation.

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