Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
541169 | Microelectronic Engineering | 2016 | 7 Pages |
Abstract
Low temperature (≤ 600 °C) polycrystalline silicon nanowires field-effect transistors have been developed following a top-down approach and classical photolithography techniques. N channel transistors have been tested with a single top-gate, bottom-gate and gate-all-around architecture in order to compare their electrical performances in relation to the interface state density. Analysis shows that surrounding gate enables control of parameters such as on-current, subthreshold slope and threshold voltage and offer potential further applications.
Graphical abstractFigure optionsDownload full-size imageDownload as PowerPoint slide
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Brice Le Borgne, Anne-Claire Salaün, Laurent Pichon,