Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
543048 | Microelectronic Engineering | 2011 | 5 Pages |
Abstract
Schemes and key technologies of wafer-level three-dimensional integrated circuits (3D IC) are reviewed and introduced in this paper. Direction of wafer stacking, methods of wafer bonding, fabrication of through-silicon via (TSV), and classification of wafer type are options for 3D IC schemes. Key technologies, such as alignment, Cu bonding, and TSV fabrication, are described as well. Better performance, lower cost, and more functionality of future electronic products become feasible with 3D IC concept application.
Graphical abstractFigure optionsDownload full-size imageDownload as PowerPoint slide
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Ming-Fang Lai, Shih-Wei Li, Jian-Yu Shih, Kuan-Neng Chen,