Evaluation of layered tunnel barrier charge trapping devices for embedded non-volatile memories

This paper presents experimental results on band gap engineered charge trapping devices for embedded non-volatile memories. Different material systems with high-k dielectrics and metal gates were fabricated using 193 nm lithography and the electrical evaluation was performed on 256 bits mini-arrays. The structure relies essentially on a layered tunnel ONO (oxide-nitride-oxide) barrier that replaces the tunnel oxide in conventional SONOS devices. In addition, we have implemented high-k dielectrics, metal gates and sealing layer in order to achieve low programming voltage and improve the data retention especially at elevated temperature. Whereas, high-k and metal gate systems allow low programme/erase voltages attractive for embedded non-volatile memories, the conventional band gap engineered SONOS (BE-SONOS) offers better high-temperature data retention. However, compared to a SONOS device with a standard “thick” tunnel oxide of 6 nm close to the EOT of the layered tunnel ONO barrier, it appears that BE-SONOS memories suffer from charge loss toward the channel and therefore we believe that the band gap engineered feature of the ONO barrier requires alternative materials.