Opportunities and challenges for Ge CMOS – Control of interfacing field on Ge is a key (Invited Paper)

Ge CMOS is very attractive for the post size-scaled Si-CMOS. However, we have to tackle a number of challenges with regard to materials and their interface control. In this paper, we discuss gate stack formation and source/drain engineering, as well as their implications for the performance of n- and p-MOSFETs. Because the Ge interface is significantly degraded by the GeO desorption occurring at a relatively low temperature (∼500 °C), it is very hard to control Ge gate stack formation by a simple thermal budget control. In addition, strong Fermi-level pinning at the Ge/metal interface is a big problem in source/drain engineering. After discussing ways to control this desorption and Fermi-level pinning at the interface in both p-FETs and n-FETs, we discuss our current status of both electron and hole mobilities.