Article ID Journal Published Year Pages File Type
6943418 Microelectronic Engineering 2015 6 Pages PDF
Abstract
(Upper) Illustration of MEMS 3D integration and wafer-level packaging with a typical TSV technology; (lower left) schematic of an ICP etch system; (lower right) a 50 μm via with 72° profile by means of ICP etch.137
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Physical Sciences and Engineering Computer Science Hardware and Architecture
Preview
Inductively coupled plasma etching of tapered via in silicon for MEMS integration
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