Low-power-consumption fully depleted silicon-on-insulator technology

Scaling the CMOS device has continuously improved its functionality and performance while lowering its power consumption and price. However, the current “scaled CMOS” technology faces several problems regarding power consumption, and a migration to new transistor structures is proceeding. “Fully depleted silicon on insulator” (FDSOI) technology can lower power consumption and improve performance of CMOS circuits with a capability of low-voltage operation. This article reviews advances in FDSOI technology: device structure, back-bias control function, fabrication process, demonstration of small variability of transistors, reliability including soft error, low voltage circuit design and silicon verification, and improvement in the energy efficiency of CMOS logic circuits. The strong requirement of further improvement in energy in the near future is finally pointed out.