A technological and electrical study of self-aligned charge-trap split-gate memory devices

Ultra-scaled self-aligned split-gate memories were fabricated with memory gate lengths of 16 nm and select gate lengths of 30 nm; charge trapping layer is Si3N4. Functionality of such memories was demonstrated, with a programming window of 6.5 V (writing) and over than 6 V (erasing) at 20 μs.